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ACT 1 Scene 1

It's an an early morning in Verilab Austin. Tommy's office. He's just picked up Davie Robinson who is visiting from the UK Verilab team. Davie's now working in the conference room with JL, while Tommy goes over his email. As he works his way through the list, a sequence of visitors arrive, either physically or via new emails or IMs:

[Davie pops his head through Tommy's office doorway]

Davie: So, when did we standardize on the VMM?

Tommy: When did we what?

Davie: The VMM. You said we standardized on it.

[JL arrives next to Davie]

JL: Why did you say we've standardized on the VMM?

Tommy: [suspicious] Who says I said we standardized on it?

Davie and JL: [together - pointing to a press release] That did!

Email from Gordon (Verilab UK): Seems we've standardized on the VMM

JL: Did you see Gordon's email?

Tommy: Hang on I'm ....

Email from Mark (Verilab Germany): I'm using OVM at the moment. Am I supposed to stop?

Tommy: %*&!$....

[Exeunt JL and Davie. Backing away, slowly]

Here's the reason for the consternation:

So now we, 60 and climbing EDA bloggers, have something to blogstorm about. JL's on it already, scooping me by five minutes. And John, at his Semi-Blog, is even gathering comments. Daniel Payne, over at Chip Design Mag, has a take too, and none too complimentary.

Daniel's general sense of underwhelmedness is understandable. But he misses one semi-important verification issue when he says, of a merger, "it really wouldn’t bring the EDA industry anything new". One thing it could do is reduce the number of SystemVerilog methodologies out there, from three to two. The three being the VMM, and let's call them: OVM_m (Mentor's OVM) and OVM_c (Cadence's OVM).